30 #define QQQdialect MPLABX 44 #undef QQQMULTIPROCESSEXH 47 #define qqqMaxBranchDepth 20 48 #define QQQstructbitmap 60 #undef QQQTEMPLATEONLY 62 #define QQQUPLOADATEND 64 #undef QQQASHLINGVITRA 66 #define qqqbitmapint unsigned int 68 #undef QQQTIC2XSERIALIO 70 #undef QQQCOMPRESSED_EXH 77 #define USB_62zzopen zzopen 79 #define USB_62zqqzqz1 zqqzqz1 82 #define FILEPOINT FILE * f, 83 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 100 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 112 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 113 #ifndef LDRA_VOID_FUNC 114 #define LDRA_VOID_FUNC 117 #if defined(QQQMAINFL) 140 #ifdef QQQ_KEEPCOMMENTS 148 #if !defined(QQQSUPPRESS_UNDEF) 154 #undef QQQHITMAP_STORAGE 156 #define qqnull_params void 157 #define QQQ_PROTOTYPE_DEF 159 #undef QQ_ANSI_PROTOTYPE 161 #define QQ_ANSI_PROTOTYPE 1 164 #define QQ_ANSI_PROTOTYPE 1 170 #define ELEMENT(N) qqqbitmapint element##N; 172 #include "USB_62zbelem.def" 176 #define ELEMENT(N) 0, 178 #include "USB_62zbelem.def" 260 #ifndef _SYSTEM_CONFIG_H 261 #define _SYSTEM_CONFIG_H 280 #define SYS_VERSION_STR "2.06" 281 #define SYS_VERSION 20600 285 #define SYS_CLK_FREQ 200000000ul 286 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 287 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 288 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 289 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 290 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 291 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 292 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 293 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 294 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 296 #define SYS_PORT_A_ANSEL 0x3F00 297 #define SYS_PORT_A_TRIS 0xFFED 298 #define SYS_PORT_A_LAT 0x0010 299 #define SYS_PORT_A_ODC 0x0000 300 #define SYS_PORT_A_CNPU 0x0020 301 #define SYS_PORT_A_CNPD 0x0000 302 #define SYS_PORT_A_CNEN 0x0021 303 #define SYS_PORT_B_ANSEL 0x10C8 304 #define SYS_PORT_B_TRIS 0x91FF 305 #define SYS_PORT_B_LAT 0x0000 306 #define SYS_PORT_B_ODC 0x0000 307 #define SYS_PORT_B_CNPU 0x0000 308 #define SYS_PORT_B_CNPD 0x0000 309 #define SYS_PORT_B_CNEN 0x0000 310 #define SYS_PORT_C_ANSEL 0xCFE1 311 #define SYS_PORT_C_TRIS 0xFFFF 312 #define SYS_PORT_C_LAT 0x0000 313 #define SYS_PORT_C_ODC 0x0000 314 #define SYS_PORT_C_CNPU 0x0000 315 #define SYS_PORT_C_CNPD 0x0000 316 #define SYS_PORT_C_CNEN 0x0000 317 #define SYS_PORT_D_ANSEL 0xC100 318 #define SYS_PORT_D_TRIS 0xFFFF 319 #define SYS_PORT_D_LAT 0x0000 320 #define SYS_PORT_D_ODC 0x0000 321 #define SYS_PORT_D_CNPU 0x0000 322 #define SYS_PORT_D_CNPD 0x0000 323 #define SYS_PORT_D_CNEN 0x0000 324 #define SYS_PORT_E_ANSEL 0xFC00 325 #define SYS_PORT_E_TRIS 0xFDFF 326 #define SYS_PORT_E_LAT 0x0000 327 #define SYS_PORT_E_ODC 0x0000 328 #define SYS_PORT_E_CNPU 0x0000 329 #define SYS_PORT_E_CNPD 0x0000 330 #define SYS_PORT_E_CNEN 0x0000 331 #define SYS_PORT_F_ANSEL 0xCEC0 332 #define SYS_PORT_F_TRIS 0xEFFF 333 #define SYS_PORT_F_LAT 0x0000 334 #define SYS_PORT_F_ODC 0x0000 335 #define SYS_PORT_F_CNPU 0x0000 336 #define SYS_PORT_F_CNPD 0x0000 337 #define SYS_PORT_F_CNEN 0x0000 338 #define SYS_PORT_G_ANSEL 0x8CBC 339 #define SYS_PORT_G_TRIS 0xDFFF 340 #define SYS_PORT_G_LAT 0x0000 341 #define SYS_PORT_G_ODC 0x0000 342 #define SYS_PORT_G_CNPU 0x0000 343 #define SYS_PORT_G_CNPD 0x0000 344 #define SYS_PORT_G_CNEN 0x0000 345 #define SYS_PORT_H_ANSEL 0x0070 346 #define SYS_PORT_H_TRIS 0xB3FB 347 #define SYS_PORT_H_LAT 0x0000 348 #define SYS_PORT_H_ODC 0x0000 349 #define SYS_PORT_H_CNPU 0x0000 350 #define SYS_PORT_H_CNPD 0x0000 351 #define SYS_PORT_H_CNEN 0x0000 352 #define SYS_PORT_J_ANSEL 0x0000 353 #define SYS_PORT_J_TRIS 0x8B7F 354 #define SYS_PORT_J_LAT 0x0080 355 #define SYS_PORT_J_ODC 0x0000 356 #define SYS_PORT_J_CNPU 0x0000 357 #define SYS_PORT_J_CNPD 0x0000 358 #define SYS_PORT_J_CNEN 0x0800 359 #define SYS_PORT_K_ANSEL 0xFF00 360 #define SYS_PORT_K_TRIS 0xFFFF 361 #define SYS_PORT_K_LAT 0x0000 362 #define SYS_PORT_K_ODC 0x0000 363 #define SYS_PORT_K_CNPU 0x0000 364 #define SYS_PORT_K_CNPD 0x0000 365 #define SYS_PORT_K_CNEN 0x0000 369 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 370 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 371 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 372 #define SYS_TMR_FREQUENCY 1000 373 #define SYS_TMR_FREQUENCY_TOLERANCE 10 374 #define SYS_TMR_UNIT_RESOLUTION 10000 375 #define SYS_TMR_CLIENT_TOLERANCE 10 376 #define SYS_TMR_INTERRUPT_NOTIFICATION false 382 #define DRV_IC_DRIVER_MODE_STATIC 385 #define DRV_SPI_NUMBER_OF_MODULES 6 388 #define DRV_SPI_POLLED 1 389 #define DRV_SPI_ISR 0 390 #define DRV_SPI_MASTER 1 391 #define DRV_SPI_SLAVE 0 393 #define DRV_SPI_EBM 1 394 #define DRV_SPI_8BIT 1 395 #define DRV_SPI_16BIT 1 396 #define DRV_SPI_32BIT 0 397 #define DRV_SPI_DMA 0 399 #define DRV_SPI_INSTANCES_NUMBER 3 400 #define DRV_SPI_CLIENTS_NUMBER 3 401 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 403 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 404 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 405 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 406 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 407 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 408 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 409 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 410 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 411 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 412 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 413 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 414 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 415 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 416 #define DRV_SPI_BAUD_RATE_IDX0 1000000 417 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 418 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 419 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 420 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 421 #define DRV_SPI_QUEUE_SIZE_IDX0 10 422 #define DRV_SPI_RESERVED_JOB_IDX0 1 424 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 425 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 426 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 427 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 428 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 429 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 430 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 431 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 432 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 433 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 434 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 435 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 436 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 437 #define DRV_SPI_BAUD_RATE_IDX1 1000000 438 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 439 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 440 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 441 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 442 #define DRV_SPI_QUEUE_SIZE_IDX1 10 443 #define DRV_SPI_RESERVED_JOB_IDX1 1 445 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 446 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 447 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 448 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 449 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 450 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 451 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 452 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 453 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 454 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 455 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 456 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 457 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 458 #define DRV_SPI_BAUD_RATE_IDX2 500000 459 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 460 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 461 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 462 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 463 #define DRV_SPI_QUEUE_SIZE_IDX2 10 464 #define DRV_SPI_RESERVED_JOB_IDX2 1 466 #define DRV_TMR_INTERRUPT_MODE true 468 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 469 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 470 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 471 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 472 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 473 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 474 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 475 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 476 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 477 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 478 #define DRV_TMR_POWER_STATE_IDX0 479 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 480 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 481 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 482 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 483 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 484 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 485 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 486 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 487 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 488 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 489 #define DRV_TMR_POWER_STATE_IDX1 491 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 492 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 493 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 494 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 495 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 496 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 497 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 498 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 499 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 500 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 501 #define DRV_TMR_POWER_STATE_IDX2 503 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 504 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 505 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 506 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 507 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 508 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 509 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 510 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 511 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 512 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 513 #define DRV_TMR_POWER_STATE_IDX3 515 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 516 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 517 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 518 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 519 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 520 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 521 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 522 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 523 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 524 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 525 #define DRV_TMR_POWER_STATE_IDX4 529 #define DRV_USART_INSTANCES_NUMBER 1 530 #define DRV_USART_CLIENTS_NUMBER 1 531 #define DRV_USART_INTERRUPT_MODE false 532 #define DRV_USART_BYTE_MODEL_SUPPORT true 533 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 534 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 542 #define DRV_USBHS_DEVICE_SUPPORT true 544 #define DRV_USBHS_HOST_SUPPORT false 546 #define DRV_USBHS_INSTANCES_NUMBER 1 548 #define DRV_USBHS_INTERRUPT_MODE true 550 #define DRV_USBHS_ENDPOINTS_NUMBER 2 553 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 555 #define USB_DEVICE_INSTANCES_NUMBER 1 557 #define USB_DEVICE_EP0_BUFFER_SIZE 64 559 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 567 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 568 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 569 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 570 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 571 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 573 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 574 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 575 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 576 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 577 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 579 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 580 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 581 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 582 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 583 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 585 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 586 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 587 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 588 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 589 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 591 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 592 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 593 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 594 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 595 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 597 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 598 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 599 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 600 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 601 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 603 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 604 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 605 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 606 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 607 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 609 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 610 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 611 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 612 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 613 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 615 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 616 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 617 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 618 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 619 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 621 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 622 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 623 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 624 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 625 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 627 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 628 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 629 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 630 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 631 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 633 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 634 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 635 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 636 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 637 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 639 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 640 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 641 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 642 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 643 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 645 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 646 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 647 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 648 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 649 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 651 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 652 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 653 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 654 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 655 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 657 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 658 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 659 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 660 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 661 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 663 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 664 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 665 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 666 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 667 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 669 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 670 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 671 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 672 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 673 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 675 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 676 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 677 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 678 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 679 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 681 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 683 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 685 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 687 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 689 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 691 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 693 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 695 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 697 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 699 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 701 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 703 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 705 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 707 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 709 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 711 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 713 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 714 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 715 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 716 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 717 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 718 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 719 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 762 #ifndef _SYS_DEFINITIONS_H 763 #define _SYS_DEFINITIONS_H 772 #include "system/common/sys_common.h" 773 #include "system/common/sys_module.h" 818 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 857 #ifndef _DRV_COMMON_H 858 #define _DRV_COMMON_H 960 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 970 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 980 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1036 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1047 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1062 #define _PLIB_UNSUPPORTED 1070 #include "system/common/sys_module.h" 1082 #define DRV_IC_INDEX_0 0 1083 #define DRV_IC_INDEX_1 1 1084 #define DRV_IC_INDEX_2 2 1085 #define DRV_IC_INDEX_3 3 1086 #define DRV_IC_INDEX_4 4 1087 #define DRV_IC_INDEX_5 5 1088 #define DRV_IC_INDEX_6 6 1089 #define DRV_IC_INDEX_7 7 1090 #define DRV_IC_INDEX_8 8 1091 #define DRV_IC_INDEX_9 9 1092 #define DRV_IC_INDEX_10 10 1093 #define DRV_IC_INDEX_11 11 1094 #define DRV_IC_INDEX_12 12 1095 #define DRV_IC_INDEX_13 13 1096 #define DRV_IC_INDEX_14 14 1097 #define DRV_IC_INDEX_15 15 1129 const SYS_MODULE_INDEX index ,
1130 const SYS_MODULE_INIT *
const init ) ;
1152 const SYS_MODULE_INDEX drvIndex ,
1197 const SYS_MODULE_INDEX drvIndex ,
1330 #ifndef _DRV_IC_STATIC_H 1331 #define _DRV_IC_STATIC_H 1332 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1333 #define DRV_IC_Close( handle ) 1372 #include "system/devcon/sys_devcon.h" 1373 #include "system/clk/sys_clk.h" 1374 #include "system/int/sys_int.h" 1375 #include "system/tmr/sys_tmr.h" 1417 #ifndef _DRV_ADC_STATIC_H 1418 #define _DRV_ADC_STATIC_H 1419 #include <stdbool.h> 1420 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1421 #include "peripheral/adchs/plib_adchs.h" 1422 #include "peripheral/int/plib_int.h" 1462 uint8_t bufIndex ) ;
1466 uint8_t bufIndex ) ;
1516 #ifndef _DRV_TMR_STATIC_H 1517 #define _DRV_TMR_STATIC_H 1566 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1567 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1568 #include "peripheral/tmr/plib_tmr.h" 1604 #ifndef _TMR_DEFINITIONS_PIC32M_H 1605 #define _TMR_DEFINITIONS_PIC32M_H 1663 #include "system/int/sys_int.h" 1664 #include "system/clk/sys_clk.h" 1683 #define DRV_TMR_INDEX_0 0 1684 #define DRV_TMR_INDEX_1 1 1685 #define DRV_TMR_INDEX_2 2 1686 #define DRV_TMR_INDEX_3 3 1687 #define DRV_TMR_INDEX_4 4 1688 #define DRV_TMR_INDEX_5 5 1689 #define DRV_TMR_INDEX_6 6 1690 #define DRV_TMR_INDEX_7 7 1691 #define DRV_TMR_INDEX_8 8 1692 #define DRV_TMR_INDEX_9 9 1693 #define DRV_TMR_INDEX_10 10 1694 #define DRV_TMR_INDEX_11 11 1705 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1790 uint32_t dividerMin ;
1792 uint32_t dividerMax ;
1795 uint32_t dividerStep ;
1811 SYS_MODULE_INIT moduleInit ;
1813 TMR_MODULE_ID tmrId ;
1817 TMR_PRESCALE prescale ;
1821 INT_SOURCE interruptSource ;
1829 bool asyncWriteEnable ;
1844 uint32_t alarmCount ) ;
1906 const SYS_MODULE_INDEX drvIndex ,
1907 const SYS_MODULE_INIT *
const init ) ;
1947 SYS_MODULE_OBJ
object ) ;
1994 SYS_MODULE_OBJ
object ) ;
2028 SYS_MODULE_OBJ
object ) ;
2082 const SYS_MODULE_INDEX index ,
2183 uint32_t counterPeriod ) ;
2673 TMR_PRESCALE preScale ) ;
2913 #ifndef _DRV_TMR_DEPRECATED_H 2914 #define _DRV_TMR_DEPRECATED_H 2955 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3019 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3084 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3143 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3204 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3263 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3324 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3354 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3386 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3417 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3449 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3511 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3576 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3593 #include "peripheral/tmr/plib_tmr.h" 3594 #include "peripheral/int/plib_int.h" 3596 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3598 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3600 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3602 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3621 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3627 static inline SYS_STATUS
3630 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3641 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3652 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3662 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3671 TMR_PRESCALE prescale ) ;
3702 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3731 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3737 static inline SYS_STATUS
3740 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3751 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3762 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3772 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3781 TMR_PRESCALE prescale ) ;
3812 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3841 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3847 static inline SYS_STATUS
3850 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3861 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3872 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3882 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3891 TMR_PRESCALE prescale ) ;
3922 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3951 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3957 static inline SYS_STATUS
3960 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3971 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3982 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3992 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
4001 TMR_PRESCALE prescale ) ;
4032 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4061 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4067 static inline SYS_STATUS
4070 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4081 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4092 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4102 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4111 TMR_PRESCALE prescale ) ;
4142 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4161 #include "peripheral/int/plib_int.h" 4203 #ifndef _DRV_PMP_STATIC_H 4204 #define _DRV_PMP_STATIC_H 4205 #include "peripheral/pmp/plib_pmp.h" 4220 PMP_DATA_WAIT_STATES dataWait ,
4221 PMP_STROBE_WAIT_STATES strobeWait ,
4222 PMP_DATA_HOLD_STATES dataHold ) ;
4277 #ifndef _DRV_USART_STATIC_H 4278 #define _DRV_USART_STATIC_H 4317 #ifndef _DRV_USART_STATIC_LOCAL_H 4318 #define _DRV_USART_STATIC_LOCAL_H 4325 #include <stdbool.h> 4362 #ifndef _DRV_USART_H 4363 #define _DRV_USART_H 4403 #ifndef _DRV_USART_DEFINITIONS_H 4404 #define _DRV_USART_DEFINITIONS_H 4410 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4411 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4448 #ifndef _PLIB_USART_H 4449 #define _PLIB_USART_H 4492 #ifndef _USART_PROCESSOR_H 4493 #define _USART_PROCESSOR_H 4502 #include <stdbool.h> 4503 #error "No Processor Family specified" 4547 USART_MODULE_ID index ) ;
4577 USART_MODULE_ID index ) ;
4609 USART_MODULE_ID index ) ;
4643 USART_MODULE_ID index ,
4644 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4673 USART_BRG_CLOCK_SOURCE
4675 USART_MODULE_ID index ) ;
4729 USART_MODULE_ID index ) ;
4759 USART_MODULE_ID index ) ;
4788 USART_MODULE_ID index ) ;
4820 USART_MODULE_ID index ) ;
4851 USART_MODULE_ID index ) ;
4893 USART_MODULE_ID index ) ;
4926 USART_MODULE_ID index ) ;
4958 USART_MODULE_ID index ) ;
4999 USART_MODULE_ID index ,
5000 uint32_t clockFrequency ,
5001 uint32_t baudRate ) ;
5042 USART_MODULE_ID index ,
5043 uint32_t clockFrequency ,
5044 uint32_t baudRate ) ;
5077 USART_MODULE_ID index ,
5078 int32_t clockFrequency ) ;
5113 USART_MODULE_ID index ,
5148 USART_MODULE_ID index ) ;
5183 USART_MODULE_ID index ,
5218 USART_MODULE_ID index ) ;
5250 USART_MODULE_ID index ) ;
5284 USART_MODULE_ID index ) ;
5317 USART_MODULE_ID index ) ;
5350 USART_MODULE_ID index ) ;
5384 USART_MODULE_ID index ,
5429 USART_MODULE_ID index ) ;
5463 USART_MODULE_ID index ) ;
5499 USART_MODULE_ID index ) ;
5536 USART_MODULE_ID index ,
5576 USART_MODULE_ID index ) ;
5614 USART_MODULE_ID index ) ;
5649 USART_MODULE_ID index ) ;
5683 USART_MODULE_ID index ) ;
5717 USART_MODULE_ID index ) ;
5750 USART_MODULE_ID index ) ;
5782 USART_MODULE_ID index ) ;
5814 USART_MODULE_ID index ) ;
5847 USART_MODULE_ID index ) ;
5881 USART_MODULE_ID index ) ;
5910 USART_MODULE_ID index ) ;
5939 USART_MODULE_ID index ) ;
5971 USART_MODULE_ID index ) ;
6003 USART_MODULE_ID index ) ;
6033 USART_MODULE_ID index ) ;
6063 USART_MODULE_ID index ) ;
6092 USART_MODULE_ID index ) ;
6121 USART_MODULE_ID index ) ;
6155 USART_MODULE_ID index ,
6156 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6188 USART_MODULE_ID index ,
6189 USART_RECEIVE_INTR_MODE interruptMode ) ;
6222 USART_MODULE_ID index ,
6223 USART_LINECONTROL_MODE dataFlowConfig ) ;
6256 USART_MODULE_ID index ,
6257 USART_HANDSHAKE_MODE handshakeConfig ) ;
6290 USART_MODULE_ID index ,
6321 USART_MODULE_ID index ) ;
6350 USART_MODULE_ID index ) ;
6381 USART_MODULE_ID index ) ;
6412 USART_MODULE_ID index ) ;
6442 USART_MODULE_ID index ) ;
6474 USART_MODULE_ID index ,
6475 USART_OPERATION_MODE operationmode ) ;
6505 USART_MODULE_ID index ) ;
6538 USART_MODULE_ID index ) ;
6567 USART_MODULE_ID index ) ;
6597 USART_MODULE_ID index ) ;
6633 USART_MODULE_ID index ) ;
6684 USART_MODULE_ID index ,
6687 bool wakeFromSleep ,
6732 USART_MODULE_ID index ,
6733 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6734 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6735 USART_OPERATION_MODE operationMode ) ;
6781 USART_MODULE_ID index ,
6782 uint32_t systemClock ,
6828 USART_MODULE_ID index ) ;
6849 USART_MODULE_ID index ) ;
6870 USART_MODULE_ID index ) ;
6904 USART_MODULE_ID index ) ;
6931 USART_MODULE_ID index ) ;
6957 USART_MODULE_ID index ) ;
6984 USART_MODULE_ID index ) ;
7010 USART_MODULE_ID index ) ;
7035 USART_MODULE_ID index ) ;
7061 USART_MODULE_ID index ) ;
7086 USART_MODULE_ID index ) ;
7112 USART_MODULE_ID index ) ;
7137 USART_MODULE_ID index ) ;
7163 USART_MODULE_ID index ) ;
7190 USART_MODULE_ID index ) ;
7216 USART_MODULE_ID index ) ;
7242 USART_MODULE_ID index ) ;
7269 USART_MODULE_ID index ) ;
7296 USART_MODULE_ID index ) ;
7323 USART_MODULE_ID index ) ;
7349 USART_MODULE_ID index ) ;
7374 USART_MODULE_ID index ) ;
7400 USART_MODULE_ID index ) ;
7427 USART_MODULE_ID index ) ;
7453 USART_MODULE_ID index ) ;
7479 USART_MODULE_ID index ) ;
7504 USART_MODULE_ID index ) ;
7529 USART_MODULE_ID index ) ;
7554 USART_MODULE_ID index ) ;
7580 USART_MODULE_ID index ) ;
7605 USART_MODULE_ID index ) ;
7631 USART_MODULE_ID index ) ;
7657 USART_MODULE_ID index ) ;
7682 USART_MODULE_ID index ) ;
7708 USART_MODULE_ID index ) ;
7733 USART_MODULE_ID index ) ;
7758 USART_MODULE_ID index ) ;
7785 USART_MODULE_ID index ) ;
7810 USART_MODULE_ID index ) ;
7836 USART_MODULE_ID index ) ;
7901 #include "system/common/sys_common.h" 7902 #include "system/common/sys_module.h" 7914 #include "system/int/sys_int.h" 7986 #ifndef _SYS_DMA_DEFINITIONS_H 7987 #define _SYS_DMA_DEFINITIONS_H 7993 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7994 #include "system/common/sys_common.h" 7995 #include "system/common/sys_module.h" 8065 #ifndef _PLIB_DMA_PROCESSOR_H 8066 #define _PLIB_DMA_PROCESSOR_H 8067 #error "Can't find header" 8111 DMA_MODULE_ID index ,
8112 DMA_CHANNEL channel ) ;
8146 DMA_MODULE_ID index ,
8147 DMA_CHANNEL channel ,
8148 DMA_CHANNEL_COLLISION collisonType ) ;
8180 DMA_MODULE_ID index ,
8181 DMA_CHANNEL channel ) ;
8213 DMA_MODULE_ID index ,
8214 DMA_CHANNEL channel ) ;
8252 DMA_MODULE_ID index ,
8253 DMA_CHANNEL channel ,
8254 DMA_CHANNEL_PRIORITY channelPriority ) ;
8283 DMA_CHANNEL_PRIORITY
8285 DMA_MODULE_ID index ,
8286 DMA_CHANNEL channel ) ;
8314 DMA_MODULE_ID index ,
8315 DMA_CHANNEL_PRIORITY channelPriority ) ;
8340 DMA_CHANNEL_PRIORITY
8342 DMA_MODULE_ID index ) ;
8372 DMA_MODULE_ID index ,
8373 DMA_CHANNEL channel ) ;
8404 DMA_MODULE_ID index ,
8405 DMA_CHANNEL channel ) ;
8434 DMA_MODULE_ID index ,
8435 DMA_CHANNEL channel ) ;
8464 DMA_MODULE_ID index ,
8465 DMA_CHANNEL channel ) ;
8496 DMA_MODULE_ID index ,
8497 DMA_CHANNEL channel ) ;
8526 DMA_MODULE_ID index ,
8527 DMA_CHANNEL channel ) ;
8558 DMA_MODULE_ID index ,
8559 DMA_CHANNEL channel ) ;
8590 DMA_MODULE_ID index ,
8591 DMA_CHANNEL channel ) ;
8620 DMA_MODULE_ID index ,
8621 DMA_CHANNEL channel ) ;
8652 DMA_MODULE_ID index ,
8653 DMA_CHANNEL channel ) ;
8682 DMA_MODULE_ID index ,
8683 DMA_CHANNEL channel ) ;
8713 DMA_MODULE_ID index ,
8714 DMA_CHANNEL channel ) ;
8744 DMA_MODULE_ID index ,
8745 DMA_CHANNEL channel ) ;
8775 DMA_MODULE_ID index ,
8776 DMA_CHANNEL channel ) ;
8806 DMA_MODULE_ID index ,
8807 DMA_CHANNEL channel ) ;
8838 DMA_MODULE_ID index ,
8839 DMA_CHANNEL channel ) ;
8870 DMA_MODULE_ID index ,
8871 DMA_CHANNEL channel ,
8872 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8901 DMA_CHANNEL_TRANSFER_DIRECTION
8903 DMA_MODULE_ID index ,
8904 DMA_CHANNEL channel ) ;
8940 DMA_MODULE_ID index ,
8941 DMA_CHANNEL channel ,
8943 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8976 DMA_MODULE_ID index ,
8977 DMA_CHANNEL channel ,
8978 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9009 DMA_MODULE_ID index ,
9010 DMA_CHANNEL channel ,
9011 uint16_t peripheraladdress ) ;
9039 DMA_MODULE_ID index ,
9040 DMA_CHANNEL channel ) ;
9071 DMA_MODULE_ID index ,
9072 DMA_CHANNEL channel ,
9073 uint16_t transferCount ) ;
9101 DMA_MODULE_ID index ,
9102 DMA_CHANNEL channel ) ;
9135 DMA_MODULE_ID index ,
9136 DMA_CHANNEL channel ,
9137 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9165 DMA_SOURCE_ADDRESSING_MODE
9167 DMA_MODULE_ID index ,
9168 DMA_CHANNEL channel ) ;
9201 DMA_MODULE_ID index ,
9202 DMA_CHANNEL channel ,
9203 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9232 DMA_DESTINATION_ADDRESSING_MODE
9234 DMA_MODULE_ID index ,
9235 DMA_CHANNEL channel ) ;
9268 DMA_MODULE_ID index ,
9269 DMA_CHANNEL channel ,
9270 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9298 DMA_CHANNEL_ADDRESSING_MODE
9300 DMA_MODULE_ID index ,
9301 DMA_CHANNEL channel ) ;
9339 DMA_MODULE_ID index ,
9340 DMA_CHANNEL channel ,
9341 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9377 DMA_MODULE_ID index ,
9378 DMA_CHANNEL channel ,
9379 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9414 DMA_MODULE_ID index ,
9415 DMA_CHANNEL channel ,
9416 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9445 DMA_CHANNEL_INT_SOURCE
9447 DMA_MODULE_ID index ,
9448 DMA_CHANNEL channel ) ;
9483 DMA_MODULE_ID index ,
9484 DMA_CHANNEL channel ,
9485 DMA_TRIGGER_SOURCE IRQnum ) ;
9520 DMA_MODULE_ID index ,
9521 DMA_CHANNEL channel ,
9522 DMA_TRIGGER_SOURCE IRQ ) ;
9553 DMA_MODULE_ID index ,
9554 DMA_CHANNEL channel ,
9555 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9582 DMA_CHANNEL_DATA_SIZE
9584 DMA_MODULE_ID index ,
9585 DMA_CHANNEL channel ) ;
9619 DMA_MODULE_ID index ,
9620 DMA_CHANNEL channel ,
9621 DMA_TRANSFER_MODE channeltransferMode ) ;
9653 DMA_MODULE_ID index ,
9654 DMA_CHANNEL channel ) ;
9683 DMA_MODULE_ID index ,
9684 DMA_CHANNEL channel ) ;
9714 DMA_MODULE_ID index ,
9715 DMA_CHANNEL channel ) ;
9744 DMA_MODULE_ID index ,
9745 DMA_CHANNEL channel ) ;
9773 DMA_MODULE_ID index ,
9774 DMA_CHANNEL channel ) ;
9804 DMA_MODULE_ID index ,
9805 DMA_CHANNEL channel ) ;
9832 DMA_MODULE_ID index ,
9833 DMA_CHANNEL channel ) ;
9869 DMA_MODULE_ID index ,
9870 DMA_CHANNEL channel ) ;
9901 DMA_MODULE_ID index ,
9902 DMA_CHANNEL channel ) ;
9935 DMA_MODULE_ID index ) ;
9964 DMA_MODULE_ID index ) ;
9994 DMA_MODULE_ID index ) ;
10023 DMA_MODULE_ID index ) ;
10052 DMA_MODULE_ID index ) ;
10082 DMA_MODULE_ID index ) ;
10110 DMA_MODULE_ID index ) ;
10138 DMA_MODULE_ID index ) ;
10166 DMA_MODULE_ID index ) ;
10195 DMA_MODULE_ID index ) ;
10223 DMA_MODULE_ID index ) ;
10257 DMA_MODULE_ID index ) ;
10287 DMA_MODULE_ID index ) ;
10317 DMA_MODULE_ID index ) ;
10346 DMA_MODULE_ID index ) ;
10381 DMA_MODULE_ID index ,
10382 DMA_CHANNEL channel ) ;
10411 DMA_MODULE_ID index ) ;
10443 DMA_MODULE_ID index ,
10444 DMA_CRC_TYPE CRCType ) ;
10475 DMA_MODULE_ID index ) ;
10505 DMA_MODULE_ID index ) ;
10535 DMA_MODULE_ID index ) ;
10565 DMA_MODULE_ID index ) ;
10594 DMA_MODULE_ID index ) ;
10624 DMA_MODULE_ID index ) ;
10653 DMA_MODULE_ID index ) ;
10683 DMA_MODULE_ID index ,
10684 uint8_t polyLength ) ;
10713 DMA_MODULE_ID index ) ;
10742 DMA_MODULE_ID index ,
10743 DMA_CRC_BIT_ORDER bitOrder ) ;
10774 DMA_MODULE_ID index ) ;
10803 DMA_MODULE_ID index ) ;
10833 DMA_MODULE_ID index ,
10834 DMA_CRC_BYTE_ORDER byteOrder ) ;
10863 DMA_MODULE_ID index ) ;
10894 DMA_MODULE_ID index ) ;
10926 DMA_MODULE_ID index ,
10927 uint32_t DMACRCdata ) ;
10958 DMA_MODULE_ID index ) ;
10991 DMA_MODULE_ID index ,
10992 uint32_t DMACRCXOREnableMask ) ;
11030 DMA_MODULE_ID index ,
11031 DMA_CHANNEL dmaChannel ) ;
11068 DMA_MODULE_ID index ,
11069 DMA_CHANNEL dmaChannel ,
11070 uint32_t sourceStartAddress ) ;
11104 DMA_MODULE_ID index ,
11105 DMA_CHANNEL dmaChannel ) ;
11143 DMA_MODULE_ID index ,
11144 DMA_CHANNEL dmaChannel ,
11145 uint32_t destinationStartAddress ) ;
11185 DMA_MODULE_ID index ,
11186 DMA_CHANNEL dmaChannel ) ;
11225 DMA_MODULE_ID index ,
11226 DMA_CHANNEL dmaChannel ,
11227 uint16_t sourceSize ) ;
11262 DMA_MODULE_ID index ,
11263 DMA_CHANNEL dmaChannel ) ;
11300 DMA_MODULE_ID index ,
11301 DMA_CHANNEL dmaChannel ,
11302 uint16_t destinationSize ) ;
11336 DMA_MODULE_ID index ,
11337 DMA_CHANNEL dmaChannel ) ;
11372 DMA_MODULE_ID index ,
11373 DMA_CHANNEL dmaChannel ) ;
11408 DMA_MODULE_ID index ,
11409 DMA_CHANNEL dmaChannel ) ;
11446 DMA_MODULE_ID index ,
11447 DMA_CHANNEL dmaChannel ,
11448 uint16_t CellSize ) ;
11482 DMA_MODULE_ID index ,
11483 DMA_CHANNEL dmaChannel ) ;
11520 DMA_MODULE_ID index ,
11521 DMA_CHANNEL dmaChannel ) ;
11560 DMA_MODULE_ID index ,
11561 DMA_CHANNEL dmaChannel ,
11562 uint16_t patternData ) ;
11606 DMA_MODULE_ID index ,
11607 DMA_CHANNEL dmaChannel ,
11608 DMA_INT_TYPE dmaINTSource ) ;
11643 DMA_MODULE_ID index ,
11644 DMA_CHANNEL dmaChannel ,
11645 DMA_INT_TYPE dmaINTSource ) ;
11681 DMA_MODULE_ID index ,
11682 DMA_CHANNEL dmaChannel ,
11683 DMA_INT_TYPE dmaINTSource ) ;
11717 DMA_MODULE_ID index ,
11718 DMA_CHANNEL dmaChannel ,
11719 DMA_INT_TYPE dmaINTSource ) ;
11753 DMA_MODULE_ID index ,
11754 DMA_CHANNEL dmaChannel ,
11755 DMA_INT_TYPE dmaINTSource ) ;
11793 DMA_MODULE_ID index ,
11794 DMA_CHANNEL dmaChannel ,
11795 DMA_INT_TYPE dmaINTSource ) ;
11828 DMA_MODULE_ID index ,
11829 DMA_CHANNEL dmaChannel ,
11830 DMA_PATTERN_LENGTH patternLen ) ;
11863 DMA_MODULE_ID index ,
11864 DMA_CHANNEL dmaChannel ) ;
11894 DMA_MODULE_ID index ,
11895 DMA_CHANNEL channel ) ;
11928 DMA_MODULE_ID index ,
11929 DMA_CHANNEL channel ) ;
11959 DMA_MODULE_ID index ,
11960 DMA_CHANNEL channel ) ;
11992 DMA_MODULE_ID index ,
11993 DMA_CHANNEL channel ,
11994 uint8_t pattern ) ;
12025 DMA_MODULE_ID index ,
12026 DMA_CHANNEL channel ) ;
12058 DMA_MODULE_ID index ) ;
12083 DMA_MODULE_ID index ) ;
12107 DMA_MODULE_ID index ) ;
12132 DMA_MODULE_ID index ) ;
12155 DMA_MODULE_ID index ) ;
12179 DMA_MODULE_ID index ) ;
12202 DMA_MODULE_ID index ) ;
12226 DMA_MODULE_ID index ) ;
12250 DMA_MODULE_ID index ) ;
12275 DMA_MODULE_ID index ) ;
12299 DMA_MODULE_ID index ) ;
12323 DMA_MODULE_ID index ) ;
12346 DMA_MODULE_ID index ) ;
12370 DMA_MODULE_ID index ) ;
12394 DMA_MODULE_ID index ) ;
12418 DMA_MODULE_ID index ) ;
12442 DMA_MODULE_ID index ) ;
12466 DMA_MODULE_ID index ) ;
12489 DMA_MODULE_ID index ) ;
12514 DMA_MODULE_ID index ) ;
12539 DMA_MODULE_ID index ) ;
12563 DMA_MODULE_ID index ) ;
12588 DMA_MODULE_ID index ) ;
12612 DMA_MODULE_ID index ) ;
12636 DMA_MODULE_ID index ) ;
12662 DMA_MODULE_ID index ) ;
12687 DMA_MODULE_ID index ) ;
12711 DMA_MODULE_ID index ) ;
12736 DMA_MODULE_ID index ) ;
12759 DMA_MODULE_ID index ) ;
12782 DMA_MODULE_ID index ) ;
12805 DMA_MODULE_ID index ) ;
12828 DMA_MODULE_ID index ) ;
12853 DMA_MODULE_ID index ) ;
12878 DMA_MODULE_ID index ) ;
12902 DMA_MODULE_ID index ) ;
12927 DMA_MODULE_ID index ) ;
12951 DMA_MODULE_ID index ) ;
12975 DMA_MODULE_ID index ) ;
12998 DMA_MODULE_ID index ) ;
13021 DMA_MODULE_ID index ) ;
13045 DMA_MODULE_ID index ) ;
13069 DMA_MODULE_ID index ) ;
13093 DMA_MODULE_ID index ) ;
13120 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13133 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13146 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13176 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13350 DMA_CRC_TYPE type ;
13356 uint8_t polyLength ;
13359 DMA_CRC_BIT_ORDER bitOrder ;
13362 DMA_CRC_BYTE_ORDER byteOrder ;
13372 uint32_t xorBitMask ;
13497 SYS_MODULE_OBJ
object ,
13498 DMA_CHANNEL activeChannel ) ;
13501 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13546 uintptr_t contextHandle ) ;
13592 const SYS_MODULE_INIT *
const init ) ;
13643 DMA_CHANNEL channel ) ;
13729 DMA_TRIGGER_SOURCE eventSrc ) ;
13807 DMA_PATTERN_LENGTH length ,
13809 uint8_t ignorePattern ) ;
14062 const void * srcAddr ,
14064 const void * destAddr ,
14066 size_t cellSize ) ;
14163 const void * srcAddr ,
14165 const void * destAddr ,
14167 size_t cellSize ) ;
14363 const uintptr_t contextHandle ) ;
14659 DMA_TRIGGER_SOURCE eventSrc ) ;
14838 SYS_MODULE_OBJ
object ,
14839 DMA_CHANNEL activeChannel ) ;
14849 SYS_MODULE_OBJ
object ) ;
14859 SYS_MODULE_OBJ
object ,
14860 DMA_CHANNEL activeChannel ) ;
14887 #define DRV_USART_INDEX_0 0 14888 #define DRV_USART_INDEX_1 1 14889 #define DRV_USART_INDEX_2 2 14890 #define DRV_USART_INDEX_3 3 14891 #define DRV_USART_INDEX_4 4 14892 #define DRV_USART_INDEX_5 5 14906 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14917 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14928 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14962 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15113 uintptr_t context ) ;
15161 USART_HANDSHAKE_MODE_FLOW_CONTROL
15165 USART_HANDSHAKE_MODE_SIMPLEX
15327 } AddressedModeInit ;
15352 = USART_ERROR_PARITY
15357 = USART_ERROR_FRAMING
15362 = USART_ERROR_RECEIVER_OVERRUN
15444 SYS_MODULE_INIT moduleInit ;
15448 USART_MODULE_ID usartID ;
15466 uint32_t brgClock ;
15482 USART_OPERATION_MODE linesEnable ;
15486 INT_SOURCE interruptTransmit ;
15490 INT_SOURCE interruptReceive ;
15494 INT_SOURCE interruptError ;
15499 unsigned int queueSizeReceive ;
15504 unsigned int queueSizeTransmit ;
15508 DMA_CHANNEL dmaChannelTransmit ;
15512 DMA_CHANNEL dmaChannelReceive ;
15516 INT_SOURCE dmaInterruptTransmit ;
15520 INT_SOURCE dmaInterruptReceive ;
15604 const SYS_MODULE_INDEX index ,
15605 const SYS_MODULE_INIT *
const init ) ;
15643 SYS_MODULE_OBJ
object ) ;
15681 SYS_MODULE_OBJ
object ) ;
15722 SYS_MODULE_OBJ
object ) ;
15763 SYS_MODULE_OBJ
object ) ;
15804 SYS_MODULE_OBJ
object ) ;
15883 const SYS_MODULE_INDEX index ,
16067 const size_t size ) ;
16260 const size_t size ) ;
16348 const uintptr_t context ) ;
16615 const size_t numbytes ) ;
16683 const size_t numbytes ) ;
16820 const uint8_t byte ) ;
17038 const SYS_MODULE_INDEX index ,
17091 const SYS_MODULE_INDEX index ,
17140 const SYS_MODULE_INDEX index ,
17355 #ifndef _DRV_USART_FEATURE_MAPPING_H 17356 #define _DRV_USART_FEATURE_MAPPING_H 17365 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17366 #define _DRV_USART_InterruptSourceEnable( source ) 17367 #define _DRV_USART_InterruptSourceDisable( source ) false 17368 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17369 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17370 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17371 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17372 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17375 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17384 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17385 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17386 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17387 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17388 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17401 #include "system/clk/sys_clk.h" 17402 #include "system/int/sys_int.h" 17440 #ifndef _SYS_DEBUG_H 17441 #define _SYS_DEBUG_H 17442 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17445 #define SYS_DEBUG_BUFFER_DMA_READY 17495 #define SYS_DEBUG_INDEX_0 0 17511 SYS_MODULE_INIT moduleInit ;
17515 SYS_MODULE_INDEX consoleIndex ;
17563 const SYS_MODULE_INDEX index ,
17564 const SYS_MODULE_INIT *
const init ) ;
17604 SYS_MODULE_OBJ
object ,
17605 const SYS_MODULE_INIT *
const init ) ;
17635 SYS_MODULE_OBJ
object ) ;
17668 SYS_MODULE_OBJ
object ) ;
17712 SYS_MODULE_OBJ
object ) ;
17755 const char * message ) ;
17805 const char * format ,
17895 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17939 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17982 #define SYS_MESSAGE( message ) 18015 #define SYS_DEBUG_MESSAGE( level , message ) 18062 #define SYS_PRINT( fmt ,... ) 18110 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18135 #define SYS_DEBUG_BreakPoint( ) 18144 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18145 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18146 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18163 #define _DRV_USART_RX_DEPTH 9 18229 const SYS_MODULE_INDEX index ,
18254 const uint8_t byte ) ;
18325 #ifndef _SYS_PORTS_H 18326 #define _SYS_PORTS_H 18365 #ifndef _SYS_PORTS_DEFINITIONS_H 18366 #define _SYS_PORTS_DEFINITIONS_H 18372 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18373 #include "system/common/sys_common.h" 18374 #include "system/common/sys_module.h" 18411 #ifndef _PLIB_PORTS_H 18412 #define _PLIB_PORTS_H 18413 #include <stdint.h> 18414 #include <stddef.h> 18479 #ifndef _PLIB_PORTS_PROCESSOR_H 18480 #define _PLIB_PORTS_PROCESSOR_H 18481 #error "Can't find header" 18531 PORTS_MODULE_ID index ,
18532 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18533 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18576 PORTS_MODULE_ID index ,
18577 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18578 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18613 PORTS_MODULE_ID index ,
18614 PORTS_ANALOG_PIN pin ,
18615 PORTS_PIN_MODE mode ) ;
18655 PORTS_MODULE_ID index ,
18656 PORTS_CHANNEL channel ,
18657 PORTS_BIT_POS bitPos ,
18658 PORTS_PIN_MODE mode ) ;
18693 PORTS_MODULE_ID index ,
18694 PORTS_CHANNEL channel ,
18695 PORTS_BIT_POS bitPos ) ;
18729 PORTS_MODULE_ID index ,
18730 PORTS_CHANNEL channel ,
18731 PORTS_BIT_POS bitPos ) ;
18768 PORTS_MODULE_ID index ,
18769 PORTS_CHANNEL channel ,
18770 PORTS_BIT_POS bitPos ) ;
18811 PORTS_MODULE_ID index ,
18812 PORTS_CHANNEL channel ,
18813 PORTS_BIT_POS bitPos ) ;
18852 PORTS_MODULE_ID index ,
18853 PORTS_CHANNEL channel ,
18854 PORTS_BIT_POS bitPos ) ;
18892 PORTS_MODULE_ID index ,
18893 PORTS_CHANNEL channel ,
18894 PORTS_BIT_POS bitPos ) ;
18929 PORTS_MODULE_ID index ,
18930 PORTS_CHANNEL channel ) ;
18965 PORTS_MODULE_ID index ,
18966 PORTS_CHANNEL channel ) ;
19003 PORTS_MODULE_ID index ,
19004 PORTS_CHANNEL channel ) ;
19041 PORTS_MODULE_ID index ,
19042 PORTS_CHANNEL channel ) ;
19079 PORTS_MODULE_ID index ,
19080 PORTS_CHANNEL channel ,
19081 PORTS_BIT_POS bitPos ) ;
19118 PORTS_MODULE_ID index ,
19119 PORTS_CHANNEL channel ,
19120 PORTS_BIT_POS bitPos ) ;
19158 PORTS_MODULE_ID index ,
19159 PORTS_CHANNEL channel ,
19160 PORTS_BIT_POS bitPos ) ;
19197 PORTS_MODULE_ID index ,
19198 PORTS_CHANNEL channel ,
19199 PORTS_BIT_POS bitPos ,
19234 PORTS_MODULE_ID index ,
19235 PORTS_CHANNEL channel ,
19236 PORTS_BIT_POS bitPos ) ;
19270 PORTS_MODULE_ID index ,
19271 PORTS_CHANNEL channel ,
19272 PORTS_BIT_POS bitPos ) ;
19306 PORTS_MODULE_ID index ,
19307 PORTS_CHANNEL channel ,
19308 PORTS_BIT_POS bitPos ) ;
19343 PORTS_MODULE_ID index ,
19344 PORTS_CHANNEL channel ,
19345 PORTS_BIT_POS bitPos ) ;
19380 PORTS_MODULE_ID index ,
19381 PORTS_CHANNEL channel ,
19382 PORTS_BIT_POS bitPos ) ;
19416 PORTS_MODULE_ID index ,
19417 PORTS_CHANNEL channel ,
19418 PORTS_BIT_POS bitPos ) ;
19452 PORTS_MODULE_ID index ,
19453 PORTS_CHANNEL channel ,
19454 PORTS_BIT_POS bitPos ) ;
19492 PORTS_MODULE_ID index ,
19493 PORTS_CHANNEL channel ) ;
19527 PORTS_MODULE_ID index ,
19528 PORTS_CHANNEL channel ) ;
19562 PORTS_MODULE_ID index ,
19563 PORTS_CHANNEL channel ,
19606 PORTS_MODULE_ID index ,
19607 PORTS_CHANNEL channel ,
19643 PORTS_MODULE_ID index ,
19644 PORTS_CHANNEL channel ,
19679 PORTS_MODULE_ID index ,
19680 PORTS_CHANNEL channel ,
19716 PORTS_MODULE_ID index ,
19717 PORTS_CHANNEL channel ,
19752 PORTS_MODULE_ID index ,
19753 PORTS_CHANNEL channel ,
19786 PORTS_MODULE_ID index ,
19787 PORTS_CHANNEL channel ) ;
19821 PORTS_MODULE_ID index ,
19822 PORTS_CHANNEL channel ,
19858 PORTS_MODULE_ID index ,
19859 PORTS_CHANNEL channel ,
19905 PORTS_MODULE_ID index ,
19906 PORTS_CHANNEL channel ,
19908 PORTS_PIN_MODE mode ) ;
19950 PORTS_MODULE_ID index ,
19951 PORTS_CHANNEL channel ,
19994 PORTS_MODULE_ID index ,
19995 PORTS_CHANNEL channel ,
20035 PORTS_MODULE_ID index ,
20036 PORTS_CHANNEL channel ,
20076 PORTS_MODULE_ID index ,
20077 PORTS_CHANNEL channel ,
20121 PORTS_MODULE_ID index ,
20122 PORTS_CHANNEL channel ,
20166 PORTS_MODULE_ID index ,
20167 PORTS_CHANNEL channel ,
20213 PORTS_MODULE_ID index ,
20214 PORTS_AN_PIN anPins ,
20215 PORTS_PIN_MODE mode ) ;
20258 PORTS_MODULE_ID index ,
20259 PORTS_CN_PIN cnPins ) ;
20303 PORTS_MODULE_ID index ,
20304 PORTS_CN_PIN cnPins ) ;
20347 PORTS_MODULE_ID index ,
20348 PORTS_CN_PIN cnPins ) ;
20391 PORTS_MODULE_ID index ,
20392 PORTS_CN_PIN cnPins ) ;
20426 PORTS_MODULE_ID index ) ;
20459 PORTS_MODULE_ID index ) ;
20495 PORTS_MODULE_ID index ,
20496 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20532 PORTS_MODULE_ID index ,
20533 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20570 PORTS_MODULE_ID index ) ;
20604 PORTS_MODULE_ID index ) ;
20640 PORTS_MODULE_ID index ,
20641 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20677 PORTS_MODULE_ID index ,
20678 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20723 PORTS_MODULE_ID index ,
20724 PORTS_CHANNEL channel ,
20726 PORTS_PIN_SLEW_RATE slewRate ) ;
20763 PORTS_PIN_SLEW_RATE
20765 PORTS_MODULE_ID index ,
20766 PORTS_CHANNEL channel ,
20767 PORTS_BIT_POS bitPos ) ;
20806 PORTS_MODULE_ID index ,
20807 PORTS_CHANNEL channel ,
20808 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20841 PORTS_CHANGE_NOTICE_METHOD
20843 PORTS_MODULE_ID index ,
20844 PORTS_CHANNEL channel ) ;
20892 PORTS_MODULE_ID index ,
20893 PORTS_CHANNEL channel ,
20943 PORTS_MODULE_ID index ,
20944 PORTS_CHANNEL channel ,
20992 PORTS_MODULE_ID index ,
20993 PORTS_CHANNEL channel ,
20994 PORTS_BIT_POS bitPos ,
20995 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21038 PORTS_MODULE_ID index ,
21039 PORTS_CHANNEL channel ,
21040 PORTS_BIT_POS bitPos ) ;
21071 PORTS_MODULE_ID index ) ;
21095 PORTS_MODULE_ID index ) ;
21119 PORTS_MODULE_ID index ) ;
21143 PORTS_MODULE_ID index ) ;
21168 PORTS_MODULE_ID index ) ;
21193 PORTS_MODULE_ID index ) ;
21224 PORTS_MODULE_ID index ) ;
21252 PORTS_MODULE_ID index ) ;
21279 PORTS_MODULE_ID index ) ;
21304 PORTS_MODULE_ID index ) ;
21331 PORTS_MODULE_ID index ) ;
21356 PORTS_MODULE_ID index ) ;
21383 PORTS_MODULE_ID index ) ;
21408 PORTS_MODULE_ID index ) ;
21436 PORTS_MODULE_ID index ) ;
21464 PORTS_MODULE_ID index ) ;
21492 PORTS_MODULE_ID index ) ;
21518 PORTS_MODULE_ID index ) ;
21544 PORTS_MODULE_ID index ) ;
21570 PORTS_MODULE_ID index ) ;
21595 PORTS_MODULE_ID index ) ;
21621 PORTS_MODULE_ID index ) ;
21648 PORTS_MODULE_ID index ) ;
21673 PORTS_MODULE_ID index ) ;
21708 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21709 #define _PLIB_PORTS_COMPATIBILITY_H 21710 #include <stdint.h> 21711 #include <stddef.h> 21746 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21763 #include "system/int/sys_int.h" 21897 PORTS_MODULE_ID index ,
21898 PORTS_CHANNEL channel ) ;
21930 PORTS_MODULE_ID index ,
21931 PORTS_CHANNEL channel ,
21961 PORTS_MODULE_ID index ,
21962 PORTS_CHANNEL channel ) ;
22000 PORTS_MODULE_ID index ,
22001 PORTS_CHANNEL channel ,
22035 PORTS_MODULE_ID index ,
22036 PORTS_CHANNEL channel ,
22073 PORTS_MODULE_ID index ,
22075 PORTS_CHANNEL channel ,
22105 PORTS_MODULE_ID index ,
22106 PORTS_CHANNEL channel ) ;
22137 PORTS_MODULE_ID index ,
22138 PORTS_CHANNEL channel ,
22170 PORTS_MODULE_ID index ,
22171 PORTS_CHANNEL channel ,
22203 PORTS_MODULE_ID index ,
22204 PORTS_CHANNEL channel ,
22238 PORTS_MODULE_ID index ,
22239 PORTS_CHANNEL channel ) ;
22279 PORTS_MODULE_ID index ,
22280 PORTS_REMAP_INPUT_FUNCTION
function ,
22281 PORTS_REMAP_INPUT_PIN remapPin ) ;
22316 PORTS_MODULE_ID index ,
22317 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22318 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22351 PORTS_MODULE_ID index ) ;
22379 PORTS_MODULE_ID index ) ;
22413 PORTS_MODULE_ID index ,
22414 PORTS_CHANGE_NOTICE_PIN pinNum ,
22446 PORTS_MODULE_ID index ,
22447 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22476 PORTS_MODULE_ID index ) ;
22505 PORTS_MODULE_ID index ) ;
22536 PORTS_MODULE_ID index ,
22537 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22568 PORTS_MODULE_ID index ,
22569 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22608 PORTS_MODULE_ID index ,
22609 PORTS_ANALOG_PIN pin ,
22610 PORTS_PIN_MODE mode ) ;
22647 PORTS_MODULE_ID index ,
22648 PORTS_CHANNEL channel ,
22649 PORTS_BIT_POS bitPos ,
22684 PORTS_MODULE_ID index ,
22685 PORTS_CHANNEL channel ,
22686 PORTS_BIT_POS bitPos ) ;
22719 PORTS_MODULE_ID index ,
22720 PORTS_CHANNEL channel ,
22721 PORTS_BIT_POS bitPos ) ;
22754 PORTS_MODULE_ID index ,
22755 PORTS_CHANNEL channel ,
22756 PORTS_BIT_POS bitPos ) ;
22789 PORTS_MODULE_ID index ,
22790 PORTS_CHANNEL channel ,
22791 PORTS_BIT_POS bitPos ) ;
22824 PORTS_MODULE_ID index ,
22825 PORTS_CHANNEL channel ,
22826 PORTS_BIT_POS bitPos ) ;
22863 PORTS_MODULE_ID index ,
22865 PORTS_CHANNEL channel ,
22866 PORTS_BIT_POS bitPos ) ;
22899 PORTS_MODULE_ID index ,
22900 PORTS_CHANNEL channel ,
22901 PORTS_BIT_POS bitPos ) ;
22934 PORTS_MODULE_ID index ,
22935 PORTS_CHANNEL channel ,
22936 PORTS_BIT_POS bitPos ) ;
22969 PORTS_MODULE_ID index ,
22970 PORTS_CHANNEL channel ,
22971 PORTS_BIT_POS bitPos ) ;
23004 PORTS_MODULE_ID index ,
23005 PORTS_CHANNEL channel ,
23006 PORTS_BIT_POS bitPos ) ;
23039 PORTS_MODULE_ID index ,
23040 PORTS_CHANNEL channel ,
23041 PORTS_BIT_POS bitPos ) ;
23074 PORTS_MODULE_ID index ,
23075 PORTS_CHANNEL channel ,
23076 PORTS_BIT_POS bitPos ) ;
23109 PORTS_MODULE_ID index ,
23110 PORTS_CHANNEL channel ,
23111 PORTS_BIT_POS bitPos ,
23194 #ifndef _DRV_SPI_DEFINITIONS_H 23195 #define _DRV_SPI_DEFINITIONS_H 23201 #include <stdint.h> 23202 #include <stdbool.h> 23203 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23204 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23240 #ifndef _PLIB_SPI_H 23241 #define _PLIB_SPI_H 23275 #ifndef _PLIB_SPI_PROCESSOR_H 23276 #define _PLIB_SPI_PROCESSOR_H 23277 #error "Can't find header" 23322 SPI_MODULE_ID index ) ;
23352 SPI_MODULE_ID index ) ;
23384 SPI_MODULE_ID index ) ;
23416 SPI_MODULE_ID index ) ;
23450 SPI_MODULE_ID index ) ;
23480 SPI_MODULE_ID index ) ;
23517 SPI_MODULE_ID index ) ;
23556 SPI_MODULE_ID index ) ;
23586 SPI_MODULE_ID index ,
23617 SPI_MODULE_ID index ,
23651 SPI_MODULE_ID index ,
23652 SPI_COMMUNICATION_WIDTH width ) ;
23687 SPI_MODULE_ID index ,
23688 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23720 SPI_MODULE_ID index ,
23721 SPI_INPUT_SAMPLING_PHASE phase ) ;
23753 SPI_MODULE_ID index ,
23754 SPI_OUTPUT_DATA_PHASE phase ) ;
23785 SPI_MODULE_ID index ,
23786 SPI_CLOCK_POLARITY polarity ) ;
23816 SPI_MODULE_ID index ) ;
23846 SPI_MODULE_ID index ) ;
23884 SPI_MODULE_ID index ,
23885 uint32_t clockFrequency ,
23886 uint32_t baudRate ) ;
23917 SPI_MODULE_ID index ) ;
23949 SPI_MODULE_ID index ) ;
23982 SPI_MODULE_ID index ) ;
24015 SPI_MODULE_ID index ) ;
24047 SPI_MODULE_ID index ) ;
24077 SPI_MODULE_ID index ) ;
24108 SPI_MODULE_ID index ) ;
24139 SPI_MODULE_ID index ) ;
24170 SPI_MODULE_ID index ) ;
24202 SPI_MODULE_ID index ,
24203 SPI_FIFO_TYPE type ) ;
24235 SPI_MODULE_ID index ) ;
24267 SPI_MODULE_ID index ) ;
24301 SPI_MODULE_ID index ,
24302 SPI_FIFO_INTERRUPT mode ) ;
24332 SPI_MODULE_ID index ) ;
24362 SPI_MODULE_ID index ) ;
24394 SPI_MODULE_ID index ,
24395 SPI_FRAME_PULSE_DIRECTION direction ) ;
24428 SPI_MODULE_ID index ,
24429 SPI_FRAME_PULSE_POLARITY polarity ) ;
24462 SPI_MODULE_ID index ,
24463 SPI_FRAME_PULSE_EDGE edge ) ;
24496 SPI_MODULE_ID index ,
24497 SPI_FRAME_PULSE_WIDTH width ) ;
24531 SPI_MODULE_ID index ,
24532 SPI_FRAME_SYNC_PULSE pulse ) ;
24564 SPI_MODULE_ID index ) ;
24594 SPI_MODULE_ID index ) ;
24626 SPI_MODULE_ID index ) ;
24656 SPI_MODULE_ID index ) ;
24686 SPI_MODULE_ID index ) ;
24716 SPI_MODULE_ID index ) ;
24747 SPI_MODULE_ID index ,
24779 SPI_MODULE_ID index ,
24811 SPI_MODULE_ID index ,
24834 SPI_MODULE_ID index ) ;
24865 SPI_MODULE_ID index ,
24866 SPI_BAUD_RATE_CLOCK type ) ;
24898 SPI_MODULE_ID index ,
24899 SPI_ERROR_INTERRUPT error ) ;
24931 SPI_MODULE_ID index ,
24932 SPI_ERROR_INTERRUPT error ) ;
24963 SPI_MODULE_ID index ,
24964 SPI_AUDIO_ERROR error ) ;
24995 SPI_MODULE_ID index ,
24996 SPI_AUDIO_ERROR error ) ;
25026 SPI_MODULE_ID index ) ;
25056 SPI_MODULE_ID index ) ;
25088 SPI_MODULE_ID index ,
25089 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25121 SPI_MODULE_ID index ,
25122 SPI_AUDIO_PROTOCOL mode ) ;
25155 SPI_MODULE_ID index ) ;
25181 SPI_MODULE_ID index ) ;
25207 SPI_MODULE_ID index ) ;
25232 SPI_MODULE_ID index ) ;
25257 SPI_MODULE_ID index ) ;
25282 SPI_MODULE_ID index ) ;
25308 SPI_MODULE_ID index ) ;
25333 SPI_MODULE_ID index ) ;
25358 SPI_MODULE_ID index ) ;
25383 SPI_MODULE_ID index ) ;
25408 SPI_MODULE_ID index ) ;
25433 SPI_MODULE_ID index ) ;
25459 SPI_MODULE_ID index ) ;
25484 SPI_MODULE_ID index ) ;
25509 SPI_MODULE_ID index ) ;
25534 SPI_MODULE_ID index ) ;
25560 SPI_MODULE_ID index ) ;
25586 SPI_MODULE_ID index ) ;
25612 SPI_MODULE_ID index ) ;
25636 SPI_MODULE_ID index ) ;
25661 SPI_MODULE_ID index ) ;
25686 SPI_MODULE_ID index ) ;
25711 SPI_MODULE_ID index ) ;
25737 SPI_MODULE_ID index ) ;
25762 SPI_MODULE_ID index ) ;
25787 SPI_MODULE_ID index ) ;
25812 SPI_MODULE_ID index ) ;
25837 SPI_MODULE_ID index ) ;
25862 SPI_MODULE_ID index ) ;
25888 SPI_MODULE_ID index ) ;
25915 SPI_MODULE_ID index ) ;
25940 SPI_MODULE_ID index ) ;
25966 SPI_MODULE_ID index ) ;
25992 SPI_MODULE_ID index ) ;
26018 SPI_MODULE_ID index ) ;
26043 SPI_MODULE_ID index ) ;
26068 SPI_MODULE_ID index ) ;
26094 SPI_MODULE_ID index ) ;
26120 SPI_MODULE_ID index ) ;
26132 #include "system/common/sys_common.h" 26133 #include "system/common/sys_module.h" 26134 #include "system/int/sys_int.h" 26135 #include "system/clk/sys_clk.h" 26136 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26174 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26186 #define DRV_SPI_INDEX_0 0 26187 #define DRV_SPI_INDEX_1 1 26188 #define DRV_SPI_INDEX_2 2 26189 #define DRV_SPI_INDEX_3 3 26190 #define DRV_SPI_INDEX_4 4 26191 #define DRV_SPI_INDEX_5 5 26203 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26452 SPI_MODULE_ID
spiId ;
26485 CLK_BUSES_PERIPHERAL
spiClk ;
26645 const SYS_MODULE_INDEX index ,
26646 const SYS_MODULE_INIT *
const init ) ;
26688 SYS_MODULE_OBJ
object ) ;
26737 SYS_MODULE_OBJ
object ) ;
26778 SYS_MODULE_OBJ
object ) ;
26843 const SYS_MODULE_INDEX drvIndex ,
27438 #include "driver/usb/usbhs/drv_usbhs.h" 27439 #include "usb/usb_device.h" 27467 #include <stdint.h> 27487 uint8_t RevNumber ;
27574 SYS_MODULE_OBJ sysTmr ;
27575 SYS_MODULE_OBJ drvTmr0 ;
27576 SYS_MODULE_OBJ drvTmr1 ;
27577 SYS_MODULE_OBJ drvTmr2 ;
27578 SYS_MODULE_OBJ drvTmr3 ;
27579 SYS_MODULE_OBJ drvTmr4 ;
27580 SYS_MODULE_OBJ drvUsart0 ;
27581 SYS_MODULE_OBJ drvPMP0 ;
27583 SYS_MODULE_OBJ spiObjectIdx0 ;
27585 SYS_MODULE_OBJ spiObjectIdx1 ;
27587 SYS_MODULE_OBJ spiObjectIdx2 ;
27588 SYS_MODULE_OBJ drvUSBObject ;
27589 SYS_MODULE_OBJ usbDevObject0 ;
27650 USB_DEVICE_HANDLE usbDevHandle ;
27651 bool deviceIsConfigured ;
27652 uint8_t configValue ;
27654 bool epDataWritePending ;
27655 bool epDataReadPending ;
27656 USB_DEVICE_TRANSFER_HANDLE writeTranferHandle ;
27657 USB_DEVICE_TRANSFER_HANDLE readTranferHandle ;
27658 USB_ENDPOINT_ADDRESS endpointTx ;
27659 USB_ENDPOINT_ADDRESS endpointRx ;
27660 uint8_t altSetting ;
27661 uint8_t byte_count ;
27759 #include <stdbool.h> 27760 #include <stdint.h> 27801 uint8_t command [ 7 ] ;
27802 bool process_complete_flag ;
27803 bool b_command_complete_flag ;
27804 bool sw_status_bit_check ;
28033 #ifndef COMMMODULE_H 28034 #define COMMMODULE_H 28040 #include "../system_definitions.h" 28181 #include <stdbool.h> 28182 #include <stdint.h> 28188 #define FIFO_RX_SIZE 7 28189 #define FIFO_TX_SIZE 7 28191 #define FIFO_ADD_OK 0 28192 #define FIFO_FULL 1 28194 #define FIFO_EMPTY 2U 28205 uint8_t * ptr_buffer ;
28210 uint8_t num_records ;
28211 uint8_t put_error ;
28212 uint8_t get_error ;
28253 uint8_t * ptrBuffer ,
28254 uint16_t Length ) ;
28341 TFifo * ptrFifo ) ;
28366 TFifo * ptrFifo ) ;
28380 #define USB_READ_BUFFER_SIZE 64 28382 #define USB_MAKE_BUFFER_DMA_READY __attribute__ ( ( coherent ) ) __attribute__ ( ( aligned ( 16 ) ) ) 28383 #define APP_EP_BULK_IN 1U 28384 #define APP_EP_BULK_OUT 1U 28422 USB_DEVICE_EVENT event ,
28424 uintptr_t context )
28426 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28428 configurationValue ;
28439 case USB_DEVICE_EVENT_RESET :
28449 case USB_DEVICE_EVENT_DECONFIGURED :
28460 case USB_DEVICE_EVENT_CONFIGURED :
28463 configurationValue = ( uint8_t * ) eventData ;
28466 *configurationValue == 1U
28478 case USB_DEVICE_EVENT_SUSPENDED :
28486 case USB_DEVICE_EVENT_POWER_DETECTED :
28495 case USB_DEVICE_EVENT_POWER_REMOVED :
28504 case USB_DEVICE_EVENT_CONTROL_TRANSFER_SETUP_REQUEST :
28510 setupPacket = ( USB_SETUP_PACKET * ) eventData ;
28513 setupPacket -> bRequest == USB_REQUEST_SET_INTERFACE
28520 USB_DEVICE_ControlStatus (
USB.
usbDevHandle , USB_DEVICE_CONTROL_STATUS_OK ) ;
28530 setupPacket -> bRequest == USB_REQUEST_GET_INTERFACE
28543 USB_DEVICE_ControlStatus (
USB.
usbDevHandle , USB_DEVICE_CONTROL_STATUS_ERROR ) ;
28551 case USB_DEVICE_EVENT_ENDPOINT_READ_COMPLETE :
28559 case USB_DEVICE_EVENT_ENDPOINT_WRITE_COMPLETE :
28567 case USB_DEVICE_EVENT_RESUMED :
28574 case USB_DEVICE_EVENT_ERROR :
28613 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 31)));
28749 USB.
endpointRx , & receivedDataBuffer[ 0 ] , sizeof ( receivedDataBuffer ) ) ;
28983 USB.
endpointRx , & receivedDataBuffer[ 0 ] , sizeof ( receivedDataBuffer ) ) ;
29037 int izzqqzz=((int)(
bitmapstruct.element5 |= (1 << 7)));
29111 #define qqqbranches 181 29112 #define QQQMAXMCDCSIZE 2 29116 #define ldra_sscanf 29132 #undef qqnull_params 29133 #define qqnull_params void 29135 #define qqzzidfield 1 29141 #define QQQFIXEDSIZE 29161 qqcptr = qqscan_str;
29163 while (qqcptr[0] ==
' ')
29169 if (qqcptr[0] ==
'-')
29175 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
29177 qqvalue = 10 * qqvalue;
29178 qqvalue = qqvalue + (qqcptr[0] -
'0');
29181 qqvalue = qqisign * qqvalue;
29207 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
29208 ldra_port_write (&ldra_buffer[0]);
29216 ldra_port_write(s);
29224 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
29225 ldra_port_write (&ldra_buffer[0]);
29233 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
29234 ldra_port_write (&ldra_buffer[0]);
29242 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
29243 ldra_port_write (&ldra_buffer[0]);
29362 static int branches_printed = 0;
29366 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
29367 ldra_port_write (&ldra_buffer[0]);
29368 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
29369 ldra_port_write (&ldra_buffer[0]);
29371 branches_printed += 8;
29391 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 29392 #define LASTELEMENT 29393 #include "USB_62zbelem.def" static int qqqstructzzopen
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
void DRV_TMR_Close(DRV_HANDLE handle)
bool Valid_Command(uchar8_t msg)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
static void Execute_System(void)
static int USB_62zqendz(int qqqi)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
static int USB_62zqqzqz(qqnull_params)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR3_DeInitialize(void)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
void SYS_DMA_Suspend(void)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
static void qqoutput(FILEPOINT char *s, int i)
uint8_t Fifo_Get(TFifo *ptrFifo)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_PMP0_Initialize(void)
static void DRV_TMR0_Open(void)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
static void Execute_Protocol_B(void)
static void Execute_Protocol_A(void)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool DRV_TMR0_Start(void)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
DRV_USART_LINE_CONTROL_SET_RESULT
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
void DRV_TMR1_Initialize(void)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
void DRV_TMR3_CounterValueSet(uint32_t value)
static void DRV_TMR4_Tasks(void)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void USB_USBDeviceEventHandler(USB_DEVICE_EVENT event, void *eventData, uintptr_t context)
void DRV_ADC0_Close(void)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void DRV_TMR0_CounterClear(void)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
static SYS_STATUS DRV_TMR2_Status(void)
static int USB_62zscanf(char *qqscan_str)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
uint8_t receivedDataBuffer [64] __attribute__((coherent))
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
void DRV_USART0_TasksError(void)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
uint8_t jobQueueReserveSize
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
static void DRV_TMR0_Close(void)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
SYS_MODULE_INIT moduleInit
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void DRV_TMR4_StopInIdleDisable(void)
SYS_DMA_CHANNEL_IGNORE_MATCH
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void DRV_TMR2_DeInitialize(void)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
void SYS_DMA_Resume(void)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
static int qqqisinitialised
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
static void DRV_TMR4_Close(void)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
void DRV_USART0_TasksTransmit(void)
void DRV_ADC_DeInitialize(void)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void DRV_TMR3_Open(void)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
static void DRV_TMR1_Open(void)
void DRV_ADC_Initialize(void)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
uint32_t DRV_TMR0_CounterValueGet(void)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
INT_SOURCE txInterruptSource
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
uintptr_t DRV_USART_BUFFER_HANDLE
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void DRV_USART0_Close(void)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void DRV_IC_Stop(DRV_HANDLE handle)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR3_Initialize(void)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
void DRV_TMR1_CounterClear(void)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
uint32_t SYS_DMA_ChannelCRCGet(void)
#define DRV_IC_Open(drvIndex, intent)
void DRV_TMR3_CounterClear(void)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_TMR4_CounterValueSet(uint32_t value)
DRV_USART_TRANSFER_STATUS
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
uint8_t DRV_PMP0_Read(void)
bool DRV_TMR2_Start(void)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void DRV_TMR3_PeriodValueSet(uint32_t value)
void DRV_TMR4_StopInIdleEnable(void)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
void APP_Initialize(void)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
bool DRV_TMR3_Start(void)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
SPI_FRAME_PULSE_WIDTH framePulseWidth
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
static void qqoutput2(FILEPOINT char *s, int i, int j)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
void SYS_DEBUG_Message(const char *message)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
bool DRV_TMR1_Start(void)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
USB_ENDPOINT_ADDRESS endpointTx
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static int USB_62zqzqzq(int qqqi)
void DRV_TMR2_StopInIdleDisable(void)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
void DRV_TMR1_StopInIdleDisable(void)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
void PLIB_USART_Enable(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t DRV_USART0_ReadByte(void)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
void SYS_DEBUG_Print(const char *format,...)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR1_Tasks(void)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_TYPE bufferType
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
void DRV_ADC1_Close(void)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
DRV_USART_BAUD_SET_RESULT
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
void(* ldra_void_function)()
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
USB_DEVICE_TRANSFER_HANDLE writeTranferHandle
static void DRV_TMR0_Tasks(void)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
uint32_t DRV_TMR2_CounterValueGet(void)
USB_DEVICE_HANDLE usbDevHandle
static void usb_watchdog(void)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
void qqqtotalupload(void)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool DRV_IC0_BufferIsEmpty(void)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
void DRV_TMR2_PeriodValueSet(uint32_t value)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
uint32_t DRV_TMR0_PeriodValueGet(void)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void DRV_TMR4_PeriodValueSet(uint32_t value)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
static void DRV_TMR2_Close(void)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR3_StopInIdleEnable(void)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
static void qqqbitmapreset(qqnull_params)
void DRV_USART0_Deinitialize(void)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
void DRV_TMR2_CounterClear(void)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
static void Fifo_Init(TFifo *ptrFifo, uint8_t *ptrBuffer, uint16_t Length)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
uint32_t DRV_TMR4_PeriodValueGet(void)
uintptr_t DRV_USART_BUFFER_HANDLE
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
static SYS_STATUS DRV_TMR3_Status(void)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
static void ValidateComm(void)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
void DRV_PMP0_Write(uint8_t data)
void DRV_TMR4_CounterClear(void)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
static void DRV_TMR2_Open(void)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_USART_Disable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
SYS_DMA_CHANNEL_CHAIN_PRIO
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
void DRV_TMR0_PeriodValueSet(uint32_t value)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
static void DRV_TMR4_Open(void)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
CLK_BUSES_PERIPHERAL spiClk
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
SYS_ERROR_LEVEL gblErrLvl
USB_DEVICE_TRANSFER_HANDLE readTranferHandle
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
static SYS_STATUS DRV_TMR1_Status(void)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
SPI_COMMUNICATION_WIDTH commWidth
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
static void qqoutput0(FILEPOINT char *s)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint16_t DRV_IC0_Capture16BitDataRead(void)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR2_StopInIdleEnable(void)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
void DRV_PMP0_ModeConfig(void)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
uint32_t DRV_TMR3_CounterValueGet(void)
static SYS_STATUS DRV_TMR0_Status(void)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void DRV_USART0_TasksReceive(void)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
bool SYS_DMA_IsBusy(void)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
static void DRV_TMR3_Close(void)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
void DRV_TMR0_CounterValueSet(uint32_t value)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
void DRV_TMR3_StopInIdleDisable(void)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
struct _DRV_SPI_INIT DRV_SPI_INIT
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
void DRV_TMR1_StopInIdleEnable(void)
uint32_t DRV_TMR4_CounterValueGet(void)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
static unsigned char qqqzzglobflag
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
bool GetDepthStatus(void)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR1_DeInitialize(void)
static SYS_STATUS DRV_TMR4_Status(void)
bool DRV_SPIn_ReceiverBufferIsFull(void)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
ldra_void_function qqqaccumupload[QQQnumfil]
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
static void DRV_TMR3_Tasks(void)
uint8_t Fifo_Length(TFifo *ptrFifo)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
uint8_t Fifo_Put(TFifo *ptrFifo, uint8_t Data)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
USB_ENDPOINT_ADDRESS endpointRx
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
#define DRV_IC_Close(handle)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR2_Initialize(void)
SPI_AUDIO_PROTOCOL audioProtocolMode
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_SPI_CLOCK_MODE clockMode
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
void DRV_IC0_Initialize(void)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
void DRV_TMR_Stop(DRV_HANDLE handle)
void DRV_TMR0_StopInIdleEnable(void)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
void DRV_TMR1_CounterValueSet(uint32_t value)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uintptr_t SYS_DMA_CHANNEL_HANDLE
SYS_STATUS DRV_USART0_Status(void)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
static struct bitmapstruct_t bitmapstruct
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void DRV_TMR0_Initialize(void)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR2_PeriodValueGet(void)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
void DRV_USART0_WriteByte(const uint8_t byte)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
static void qqqupload(qqnull_params)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
INT_SOURCE rxInterruptSource
void SYS_PORTS_Initialize()
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
static void qqqqinitialise(int ii)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
bool DRV_TMR_Start(DRV_HANDLE handle)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void DRV_TMR1_PeriodValueSet(uint32_t value)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
static void DRV_TMR2_Tasks(void)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
INT_SOURCE errInterruptSource
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
uint32_t DRV_TMR1_CounterValueGet(void)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
ldra_void_function qqqaccumreset[QQQnumfil]
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void DRV_TMR4_Initialize(void)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR3_PeriodValueGet(void)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR1_PeriodValueGet(void)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
DRV_SPI_TASK_MODE taskMode
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
DRV_USART_LINE_CONTROL_SET_RESULT
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
static void DRV_TMR4_DeInitialize(void)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
bool DRV_TMR4_Start(void)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
void DRV_TMR2_CounterValueSet(uint32_t value)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
static int qqqqbmselwidth
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_USART_Close(const DRV_HANDLE handle)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
static void DRV_TMR0_DeInitialize(void)
SPI_FRAME_SYNC_PULSE frameSyncPulse
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
bool DRV_USART0_TransmitBufferIsFull(void)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
static void Execute_Auto_Protocol_A(void)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_IC0_Capture32BitDataRead(void)
static void DRV_TMR1_Close(void)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)